Softrock Lite 6.2
Adventures in Electronics and Radio
Elecraft K2 and K3 Transceivers
Measuring 60 Hz
One project I've started requires measuring the 60 Hz
power line frequency with reasonable accuracy. This turns out to be more
complicated than one might think. There are two main issues:
- Obtaining an isolated sample of the line voltage
- Measuring the frequency
For safety reasons, it's essential to isolate the measuring
instrument's electronics from the power line. I've spent some time looking at
isolation methods, such as a transformer, or optical couplers. Since line
frequency by itself is not all that interesting, the same measurement system
should also capture line voltage. This means that we need a voltage sample free
of artifacts such as flat topping or dead bands around zero crossing.
These reasons, amongst others, make another approach more
attractive�making a direct connection to the power line, but isolating the
associated electronics from the rest of the instrument with optical isolators.
I'll have more to say about these aspects of the project as it further develops.
The most obvious method of determining frequency is to count the number of zero
crossings in a specific time period or "gate." The simplest implementation of
this technique permits resolution of 1/gate period, i.e., with a 1 second gate,
we can resolve the input frequency to 1 Hz, and with a 10 second gate to 0.1 Hz,
etc. There are clever ways to improve this resolution via interpolation, but
another approach is to measure the period of one or more cycles. Since
frequency is the reciprocal of period, it's simple to obtain frequency from
To measure period, the normal method is to use a high
frequency auxiliary signal and count the number of auxiliary pulses during a
period. In essence, this reverses the signal and gate functionality in the
normal counter arrangement.
My work is with a PIC18F4620 microcontroller, with a 40
MHz clock. Using its internal counter/timer functionality, the high frequency
auxiliary signal is one instruction cycle, one-fourth the clock or 100 ns. A 60
Hz signal has a period of 16.6666... milliseconds, or, measured in terms
of instruction cycles or "ticks," 166,666.666...ticks. With an error of ±1 tick
at the start and end of the gate period, theoretically we can determine the
input period with an error of about 1 part in 80,000, or 0.0012%. This assumes
there are no error sources in the rest of the circuitry, of course, so it is a
highly optimistic target.
Our algorithm in pseudo-code is:
Set counter = 0
Wait for a zero crossing
Until 2nd zero crossing
Each counter increment represents 100 ns in the
18F4620 operating with a 40 MHz clock. There are a few details to be taken care
of in this approach, including the fact that the 18F4620 counters are only
16 bits wide, and we need 18 bits to measure a full cycle's period at 50 or 60
Hz, but these are details not too hard to deal with.
The tricky part is the "wait for zero
crossing" appearing in both the start and stop portions of the algorithm. There
is an excellent review of a variety of methods of detecting power line zero
Wall, Simple Methods for Detecting Zero Crossing well worth reading.
In the course of working on algorithms, so far I've been
working with a relatively simple arrangement, illustrated below.
V2 is an accurate 60 Hz signal source, in this case from a
Telulex SG-100 digital function generator. It is set to output 60.00 Hz at 3.0
volts peak-to-peak. This means, of course, that V2's instantaneous voltage
ranges from +1.5 to -1.5 volts. This is an inconvenient range to work with, so
U1 is a level shifter, centered around 2.5 volts. U1's instantaneous output
therefore ranges from 1.0 v to 4.0 volts, a range more compatible with
microcontrollers and A/D converters.
In order to
measure the period, we wish to convert the input sine wave to logic levels�0
when the V2 is negative and +5 volts when it is positive. Since we've shifted
V2's reference by 2.5 volts, one way to accomplish the digital conversion is to
use an op-amp running open loop as a comparator, as is done in U2. One
input is biased at +2.5V whilst the other has the level shifted 60 Hz input
signal. When the level shifted 60 Hz signal is less than 2.5 V, U2 saturates
positive at +5V output and when it is less than 2.5 V, U2 saturates negative, or
0 V output.
I originally used a real comparator, an LM311, instead of
an op amp. Comparators are faster than op-amps and are tolerant of high
differential voltages between the inputs. In this case, the MCP6021 is tolerant
of the input voltage differential. More importantly, so far my circuit is
on a plug-in solderless breadboard and the LM311's fast output transitions
produce unwanted spikes and ringing. The slower MCP6021 is an advantage in this
case. When it comes time to make the prototype PCB, I'll revisit the true
comparator versus op-amp open loop choice.
The oscilloscope capture below shows U2's output. No gross
ringing or overshoot.
Running U2's output into the 18F4620 Timer0's input, with
some suitable Swordfish code, produced the following frequency distribution.
This breadboard uses a ceramic resonator as a time
base, so the absolute frequency is not accurate. More importantly, however, is
the standard deviation; 0.0173 Hz, or 1 part in 3500. this is perhaps 20 time
worse than our theoretical maximum accuracy.
More usefully for analysis purposes is the period
information, presented below. We see jitter in the zero crossing of nearly 5 µs
To assure you that the SG-100 function generator is stable
and accurate, I also made period measurements using a Racal 1992 frequency
counter. Plotted with the same horizontal scale (50 microseconds range) the
difference is obvious. The problem resides with the test circuitry and/or
software, not the SG-100. (Compute the frequency from the average
period�60.00060 Hz is the answer.)
Why the PIC results show nearly a 5 µs period jitter
(standard deviation) becomes clearer when we look at the MCP6021 slicer's output
waveform. Using the "variable persistence" mode of a Tektronix TDS430 digital
oscilloscope, we see that what appears to be a crisp, fast transition,
when expanded in time, is actually an ensemble of transition waveforms. (I
collected the data with persistance = 5.00 seconds.) I'm using a TTL-compatible
pin in the 18F4620 t o sense the input, so we can look at the spread or smear
around +0.8V for the 0→1 transition and around 2.5V on the 1→0 transition.
We see several microseconds jitter in both cases. Even if we concentrate on
the darkest portion of the trace, representing the most common
transitions, we still see more than 2 µs jitter. If we consider that the jitter
is an issue on both the 0→1 and 1→0 transitions, these values can be doubled.
And, at the moment, my algorithm makes separate measurements of positive and
negative half-cycles, so there are a total of four transitions subject to
jitter. As an eyeball average and statistical view of the oscilloscope traces,
I'll guess that the standard deviation of each transition is around 2 µs and
that the individual jitter values are randomly distributed.
The variance is the square of the standard deviation, or 4
µs, so the variance of four transitions used in the measured period data is 16
µs. The standard deviation of the four transitions considered in series is
therefore the square root of the variance or 4 µs. Considering the rough nature
of the jitter estimate, this is not bad agreement with the measured 4.85 µs
Another way of looking at the 4.85 µs jitter is to estimate
what voltage error or noise it corresponds to.
slope of a sine wave with angular frequency ω and amplitude A (A sin(ωt)) can be
estimated by differentiating it at the zero crossing point. The derivative is Aω
cos(0) or Aω. In the test signal, A = 1.5 V and ω is 2πf where f = 60 Hz, which
is 565.5 volts/sec. We can assume for small time periods the derivative is
close to the differential ΔV/Δt. Hence, 4.85 µs corresponds to a voltage or
noise value of 4.85 x 10-6 sec x 565 V/sec = 1.3 millivolts.
This is a reasonable amount of noise considering the noise
problems inherent in solderless plugboards. It also suggests that a low noise
PCB layout should improve our noise performance and hence reduced jitter in the
I'll update this page as I have more to say about the